IAR Visual State

IAR visualSTATE is a set of highly sophisticated and easy-to-use development tools for designing, testing and implementing embedded applications based on state machines.

It provides advanced verification and validation utilities and generates very compact C/C++ code that is 100% consistent with your system design. In addition, the new and revolutionizing integration with IAR Embedded Workbench, a fully integrated C/C++ compiler and debugger toolset, enables true state machine debugging on hardware—get direct graphical feedback on various levels of detail.

Highlights

Generation of human-readable code
Build integration with IAR Embedded Workbench
Verificator improvements
Logging to test sequence files
Updated user guides

Key features

Completely integrated development environment including a graphical designer, test tools, a code generator, and a documentation facility.
Graphical state machine design based on the Unified Modeling Language (UML) state machine subset
Formal verification of the design model to find unwanted properties in the design, like dead-ends or unreachable states etc.
Test and validation tools to ensure at an early stage of design that the application behaves as expected, even before the hardware exists.
Automatic code generation providing very compact C/C++ code, 100% compliant with the design.
Automatic documentation generation with comprehensive information.
Tightly integrated with IAR Embedded Workbench, ready-made project examples for various microcontrollers and evaluation boards

Benefits of model-driven design

Design an embedded application by drawing objects, events, actions etc, using the powerful notation of hierarchical UML state charts and state machines.
Discuss the design and exchange ideas with others thanks to the model-driven design approach and the graphical design representation.
Simulate and visualize your application to find mistakes early in the design cycle.
Verify the logical consistency of your designs run-time model with the extremely powerful formal verificator.
Perform extensive tests continuously and iteratively throughout your development: validation of the state machine behavior, regression testing and automatic test coverage reporting.
Use the C-SPY® extension to do high-level debugging on hardware with feedback in the design domain, instead of fighting with low level implementation details.
Automatically generate error-free micro-tight C/C++ code that is 100% consistent with your design.
Easily add new functionality to an existing application as market requirements change.
Maintain an existing application thanks to the accurate, structured documentation that is always in-sync with the final design.

Navigator

The Navigator is used for the overall handling of your embedded development project. From here you can launch the other modules of visualSTATE and you can specify settings for the Verificator and the Coder.

The Navigator contains a tree browser where you can see the file structure of your workspace. A workspace is a file that contains one or more projects with systems and state chart files. The main window has links to support, documentation, release notes etc. and the bottom window shows the properties of the loaded workspace.

After creating a project in the Navigator you are ready to go to the Designer to draw your state machine models.

Designer

The Designer is a state-of-the-art tool for designing state machines. The tree browser allows you to overview and navigate through your embedded project. All elements of the system are visible and accessible through the browser, and a double-click on the desired element brings up the appropriate configuration dialog box on the screen

In the main window you create your state machine model using states, transitions, events, actions, initial states, variables, assignments, concurrent regions, unit states, history states, deep history states, guards, signals, parameters, entry, exit, and do reactions—according to the UML notation.

To give your state machine designs maximum clarity you have the option to individually color and size all drawing objects. This makes it possible to distinguish between for instance normal operation and error handling in your application.

The use of state machines enables a truly interactive and iterative working model where you begin with an outline of your application, and then step-by-step add functionality at a more detailed level. It is possible at any time to simulate the behavior of the model using the visualSTATE Validator, and you can also create a prototype or target implementation whenever you want.

Verification

Click here

Validator

To find out whether your state machine design behaves as intended, you use the Validator. You test and validate your application by sending events into the design model, and in the different windows you can see the results of the events. The validator can also use the Designer to animate the applications response directly on your state machine diagram.

Test sequences can be recorded to a log file. The log file can be replayed later so you can carry out exactly the same sequence of test steps. visualSTATE automatically detects if any behavioral changes have been made in the model. For fine-grained debugging control during simulation, breakpoints can be set on the activation of states, transitions, variables and action functions.

Dynamic analysis

The dynamic analysis tool is used to calculate the exact test coverage and to profile your application. The analysis is based on a test sequence log file from a simulation, prototype execution or target execution. By invoking the dynamic analysis tool visualSTATE will calculate how many times certain events, actions, signals, variables and state-transitions have occurred. It will also identify and pinpoint any unexecuted parts of the application

Static analysis

With the Static Analysis tool you can ask questions about your state machines behavior. You can analyze the system from either the event or the action side. For example, if you ask, "What can happen when the button A event is received?"the analysis tool will report all possible state-transitions and actions triggered by this particular event. The same analysis can be made for a specific actionlike "what can clear the display?" visualSTATE will immediately report all possible state-transitions, which cause that particular action

RealLink

The RealLink feature of visualSTATE allows you to communicate with the target over a standard communication interface, like RS-232, CAN or Ethernet. This way you can monitor and control the run-time behavior of the model directly in the target application.

By using the Graphical Back Animation feature and connecting RealLink to the visualSTATE environment, the behavior of the target can be monitored graphically in the visualSTATE Designer. It is also possible to re-run previously logged scenarios and to execute test vectors from the host computer.

C-SPYLink

C-SPYLink bridges visualSTATE and IAR Embedded Workbench to make true high-level state machine debigging possible directly in C-SPY, in addition to the normal C level symbolic debugging.

C-SPYLink offers the following main features:

The complete global state of the state machine system can be monitored live.
State machine level breakpoints. Breakpoints can also be set on specific events or signals.
A choice between execution at nearly full speed with periodic updating of the IAR Embedded Workbench IDE windows or at maximum speed without window updates.
No extra user-written support code for communication, configuration of port protocols, etc., is needed.

Prototyping

The prototyping concept of visualSTATE makes your communication with marketing and customers much easier. It will help you increase the awareness and knowledge of your product before it is launched. Your sales force and technical support staff will already be well acquainted with the product and able to introduce the product on the market rapidly.

Already at a very early stage of a development project it is possible to have marketers and customers try out the new product and give important feedback. This reduces the number of last-minute changes significantly. You will only have to do the design work once. The design model used in your prototype is the very same as the one used in your final product. Thanks to the unique technology in visualSTATE, your final product will behave in a way 100% identical to that of your prototype.

Together with visualSTATE you get an interface connector to Altia FacePlate and Altia Design, a drag and drop simulation graphics tool. With this interface connector, you can build your graphical prototype with Altia and with simple drag and drop connect the graphics to your visualSTATE design. In this way you can simulate and test your design together with a realistic graphical user interface.

And if you are only reasonably fluent in using a windowing library of your choice for your PC environment, you can easily create a mock version of the user interface using your favorite PC IDE. This user interface communicates with the state machine model in the same manner as your target hardware, while running both the user interface and the state machine model on the PC.

Coder

IAR visualSTATE generates code for your embedded state machine design automatically. This gives you the benefit of having control logic code that is 100% consistent with the design. visualSTATE employs a technology that ensures fully deterministic execution of your state machine code. Both execution time and sequence are deterministic. There is no possibility for race conditions to occur when executing concurrent hierarchical state machines in the visualSTATE implementation model. This means that your product will always behave the same.

The technique used by visualSTATE ensures that the generated code is fully consistent with your design. Every time you invoke the visualSTATE Generator to generate your code, it is always built from scratch—based only on the current design. No legacy of older versions of the design will remain.

The code generated by visualSTATE is in ISO/ANSI C or C++ source code. This gives you maximum flexibility in porting the application to a specific target.

One key concern for many developers is code size. Thanks to the well-thought method of code generation and implementation, applications based on visualSTATE will typically occupy less code and data space than a corresponding handwritten application. This means that visualSTATE is well suited even for 8- and 16-bit targets.

Integration

Now the generated code must be integrated into the target application. The generated code will execute the control logic defined in the state chart diagrams. The code is ready to be used in target, but it must be combined with a user-written main loop that can interpret it. You must also implement device drivers for capturing the events. visualSTATE includes two APIs that function as the interface between the user-written code and the Coder-generated files.

If you want to run a visualSTATE application under a real-time operating system, then you have several options—depending on your system architecture. The basic method for implementation of a visualSTATE application is to run the application logic as one task. The firmware layer, and other parts of your application can be run in the same task or in any other task; the choice is yours. A more advanced method for implementation is to run the generated visualSTATE application in several tasks. You can then map each subsystem to a specific task.

By using any ANSI C compiler, you will compile, link and locate the generated code together with your firmware, and the outcome is a complete executable application for your target platform.

Documenter

With the Documenter you can easily create an up-to-date documentation report on your visualSTATE project. The report includes information on design, validation, simulation, verification, generated code and implementation. All relevant project information is collected from the other visualSTATE modules and organized into a structured document in Rich Text Format or HTML.

Within the Documenter you can specify which information you want to include in the documentation report, and you can choose between various levels of detail for your report.